Recently, as the market for mobile phones is increasing, there is an increasing demand for the semiconductor for mobile devices, termed a random access memory for mobile equipment (referred to below as “mobile RAM”). In general, the mobile RAM is routinely presented as a multi-chip package (MCP) along with an application CPU or a flash memory.
As one of the characteristics of the mobile RAM, it has low power characteristics superior to the routine RAM. As an example, the mobile RAM has a low power mode, termed a deep power down mode (see, for example, the Patent Publications 1 and 2). When the operating mode of the mobile RAM enters the deep power down mode, the mobile RAM substantially interrupts the power supply line within the RAM to lower the power consumption in the RAM to a lowermost value possible. In actuality, only an initial-stage input circuit and a portion of the power supply circuit are in operation, while the RAM information is not retained, with the current consumption being 10 μA or less.
An input unit in this mobile RAM will now be explained. FIG. 5 depicts a block diagram of an input section in a conventional mobile RAM. The input section in the mobile RAM includes an external input terminal 113, an input capacitance adjustment capacitor 112, an initial stage input circuit 114, static charge breakdown prohibiting semiconductor devices 117 to 120, and a static charge breakdown prohibiting resistor device 121. In this input section, signals entered to the external input terminal 113 are entered to the initial stage input circuit 114 via resistor device 121. The elector-static noise, applied to the external input terminal 113, is attenuated in the semiconductor devices 117 to 120 and in the resistor device 121, so as not to damage the initial stage input circuit 114 or the input capacitance adjustment capacitor 112. The semiconductor devices 117 to 120 are made up e.g. by diodes or MOS transistors, and operate for becoming conductive upon incoming of a signal in excess of a preset voltage level, to conduct the current to the ground.
Meanwhile, e.g., the semiconductor devices 117 to 120 and the static charge breakdown prohibiting resistor device 121 possess non-negligible capacitances. By and large, the capacitance value of an input terminal of a semiconductor IC is prescribed at relevant electrical rating values. Hence, the input capacitance adjustment capacitor 112 for confining the input terminal capacitance within the range of prescribed values is added to the input terminal, under the assumption that departure from design capacitance values may possibly arise due, e.g., to process variations occurring in the course of manufacture. With a double data rate synchronous DRAM (DDR SDRAM), for example, the prescriptions for the input terminal capacitances are 2.5 pF to 3.5 pF. Thus, a plurality of the input capacitance adjustment capacitors 112, the input capacitance values of which can be adjusted at steps of the order of 0.1 pF, are connected across an input end of the initial stage input circuit 114 and the ground. There is provided a built-in structure for adjusting the capacitance by selecting and connecting plural capacitors by, e.g., switching the interconnections. The input capacitance adjustment capacitors 112 are each arranged so that the total capacitance thereof will amount to approximately 0.5 pF to 1 pF.
[Patent Publication 1] JP Patent Kokai Publication No. JP-P2003-133935A (FIGS. 1 and 2)
[Patent Publication 2] JP Patent Kokai Publication No. JP-P2004-39205A (FIG. 1)